The continuing popularity of portable electronic devices presents manufacturers with significant challenges. Increasing capability of electronic devices is moderated by considerations of cost, size, weight, and battery life. These considerations have increasingly resulted in higher levels of semiconductor integration. Thus, portable electronic devices frequently embed memory, control, signal processors, and other circuit functions on a single integrated circuit. Further optimization of these portable electronic devices dictates even greater reduction in geometric feature sizes and spaces between these geometric features. Geometric feature size and space reduction of semiconductor integrated circuits, however, is limited by state-of-the-art fabrication equipment. Reduction of geometric feature sizes and spaces beyond manufacturing equipment capability inevitably results in short or open circuit conditions of the multi-layer geometric features. These short or open circuit conditions often render the semiconductor integrated circuit inoperable, thereby degrading yield, the functional fraction of total semiconductor integrated circuit product. The degraded yield, therefore, must be balanced against feature size and space reduction in an effort to minimize size and cost of the semiconductor integrated circuit.
Semiconductor integrated circuit manufacturers constantly strive to optimize layout of geometric features of semiconductor integrated circuits to reduce overall size without degrading yield. For example, Fukaura et al., A Highly Manufacturable High Density Embedded SRAM Technology for 90 nm CMOS, IEDM Technical Digest, 2002, disclose two types of memory cell layouts to achieve a target memory cell size. The Type A cell of Fukaura et al. is reproduced as cell 300 of FIG. 3 together with five other cells. The memory cells are placed in various views to form an array of memory cells. These memory cells are aligned vertically and horizontally with adjacent cells in the array. This alignment facilitates straight interconnections such as bitlines, wordlines, and power lines between cells. These straight interconnections are generally shorter and may have less parasitic capacitance and resistance than alternative designs with multiple bends and corners. There are generally eight views as shown at FIG. 1. Each view is illustrated as an upper case “F”. View V1 of FIG. 1 is rotated 90 degrees counter clockwise to form view V2. Views V3 and V4 are each rotated another 90 and 180 degrees counter clockwise, respectively. View V5 is a mirror image about a vertical axis of view V4. Views V6, V7, and V8 are formed by rotating 90, 180, and 270 degrees counter clockwise from view V5.
Referring now to FIG. 4, the views of the memory array of FIG. 3 will be explained in detail. Memory cell 300 in the upper left corner of the memory array is placed in view V1. Due to the layout of memory cell 300, view V1 is identical to view V3 as indicated by FIG. 4. Cell 302 is placed below cell 300 in view V6, which is identical to view V8. View V6 is formed by rotating view V1 180 degrees counter clockwise and placing a mirror image about a vertical axis. Cell 304 is placed below cell 302 in view V1. Memory cells 300, 302, and 304, therefore, form a first array of memory cells. Cells 306, 308, and 310 form a second array of memory cells that is adjacent and aligned with the first array of memory cells. Cells 306, 308, and 310 are placed to the right of cells 300, 302, and 304 in views V6, V1, and V6, respectively. Thus, the same placement views are used in both the first and second arrays of memory cells. Views V6, V1, and V6 of cells 306, 308, and 310 are formed as a mirror image about a vertical axis of cells 300, 302, and 304, respectively. These views permit each cell to share other geometries with adjacent cells, thereby conserving layout area as will be explained in detail. Furthermore, these conventional memory cells of the prior art are placed in an array in rows and columns so that they are aligned with each other in the horizontal and vertical directions.
Turning now to FIG. 2, the electrical circuit corresponding to exemplary memory cell 302 of the prior art will be explained in detail. Each memory cell of FIG. 3 is electrically identical to the schematic diagram of FIG. 2. Moreover, the geometric layout of each memory cell of FIG. 3 is substantially identical except that they may be placed in different views as previously explained. Memory cell 302 is bounded above and below by memory cells 300 and 304 as indicated by the solid line cell boundaries. Memory cell 302 includes a latch formed by P-channel load transistors 201 and 202 formed in N-well region 222 and N-channel drive transistors 203 and 204 formed over P-substrate regions outside N-well region 222. These transistors are indicated by polycrystalline silicon gate regions crossing an active region. Here, an active region is formed between isolation regions and may be P+, N+, or a lightly doped channel region under a polycrystalline silicon gate region. Source terminals of P-channel load transistors 201 and 202 are connected to positive Vdd supply voltage in metal (not shown) at metal-to-P+ contact areas 212. Likewise, source terminals of N-channel drive transistors 203 and 204 are connected to ground or Vss supply voltage in metal (not shown) at metal-to-N+ contact areas 214. Each of the metal-to-silicon contact areas 212 and 214 is formed by a half contact in each of two adjacent cells. Output terminals 216 and 218 of the latch are indicated at FIG. 3 as metal-to-N+ contact areas. These output terminals 216 and 218 are connected to access N-channel pass transistors 205 and 206, respectively. Gates of the N-channel pass transistors 205 and 206 are connected to word line 220 indicated by a dashed line. The other terminals of N-channel pass transistors 205 and 206 are connected to bit line BLA 208 and complementary bit line /BLA 210 indicated by dotted lines, respectively.
Referring to FIG. 3, there is a layout diagram of the prior art corresponding to the schematic diagram of FIG. 2. Fukaura et al. disclose the minimum size of this cell is determined by the design rules listed at Table 1. In general, any of these design rules may limit the horizontal or vertical dimensions of the memory cell. As such, these limiting design rules are critical dimensions and may not be further reduced without increasing the probability of shorting. Two critical dimensions are indicated at FIG. 3 between cells 300 and 306 which limit the size of individual memory cells. A first critical dimension is distance P1 between adjacent polycrystalline silicon geometries 250 and 252. These geometries are collinear. Because they are aligned end-to-end they cannot be moved closer together without increased shorting of the polycrystalline silicon geometries and decreased yield. A second critical dimension is the distance C1 between metal-to-silicon contact 254 and metal-to-polycrystalline silicon contact 256. A reduction in this distance C1 may result in a metal-to-metal short even if it is possible to reduce distance P1. Thus, the individual memory cell size and corresponding array size are limited by these critical dimensions.
FIGS. 5A and 5B illustrate the symmetry of conventional memory cells of the prior art. The memory cells are placed in view V1. A vertical line Y—Y separates the left and right halves of the memory cell of FIG. 5A. If the right half is rotated 180 degrees and placed on top of the left half, all geometrical layers are aligned. The half contact 502, for example, is aligned with the half contact 500. The top and bottom halves of the cell of FIG. 5B are separated by horizontal line X—X. If the bottom half is rotated 180 degrees and placed on top of the top half, all geometrical layers such as half contacts 506 and 504 are again aligned. Each half of the conventional memory cell of the prior art, therefore, is symmetrical with the other half of the memory cell.